Surge suppressor devices are well known and widely utilized in the semiconductor arts. These devices, typically discrete devices, are employed to suppress transients of high currents in a power supplies or the like before the transients reach and potentially damage an integrated circuit or similar structure. Surge suppressor devices find uses in both high and low voltage applications although they are particularly useful for low voltage applications of 7 volts or less.
It is well known to employ discrete reference diodes as surge suppression devices in low voltage applications. These reference diodes are planar structures and typically fabricated in single crystal silicon substrates. The diodes are often boron doped and require an extremely steep junction gradient. They have extremely shallow junction depths (usually of less than 1 micrometer) and their highest dopant concentration is near the surface of the device. Accordingly, breakdown occurs very near the device surface. This causes the diodes to be vulnerable to oxide/silicon interface states and/or dominant silicon trapping states. This results in high leakage.
Surface defects often caused by chemical/mechanical polishing, implanting steps and the like are prevalent in shallow junction reference diodes. The surface defects in the diodes cause leakage and form "hot spots" at the areas where the defects are located. These "hot spots" cause the diode junction to burn up which keeps the diode from suppressing transients. Hence, low surge capability.
It has previously been attempted to use a fast diffusing dopant such as aluminum to create diodes having a deeper junction. However, the aluminum causes significant material defects within the silicon substrate. Large densities of material defects and other interstitials within the substrate result in excessive reverse leakage and low surge capability.
U.S. Pat. No. 4,484,206 issued to Moroshima et al. on Nov. 20, 1984 and titled "Zener Diode With Protective PN Junction Portions" teaches a zener diode that exhibits a high endurance characteristic against surge voltages. This planar device is fabricated with the use of 2 masks to implant P regions of differing dopant concentrations. A shallow P+ region will have sub-surface breakdown but the shallow junction is vulnerable to charging effects at silicon/oxide interfaces as well as substrate defects.
In their paper titled "A Proposed Planar Junction Structure With Near-Ideal Breakdown Characteristics", IEEE Electron Device Letters, Vol. EDL-6 No. 9, September, 1985, Ahmad et al. teach the addition of a low-concentration P type pocket around the edge region of a P+-N planar junction to improve electric field distribution. The planar structure taught includes a shallow P+ region, shallower than the low-concentration P pocket. These P regions are formed in a substrate, not in epitaxial material. This structure is vulnerable to material defects in the substrate as well as charge effects.
Accordingly, it would be highly desirable to have a surge suppression structure having good surge capability, not vulnerable to substrate defects and capable of operating at relatively low voltages.